NSN 5962-01-310-5753
Part Details | DIGITAL MICROCIRCUIT
5962-01-310-5753 A microcircuit specifically designed to generate, modify, or process electrical signals which operate with two distinct or binary states. These states are commonly referred to as on and off, true and false, high and low, or "1" and "0".
Alternate Parts: CD54HCT4046AF3A, CD54HCT4046AF/3A, 77A110638P001, 5962-01-310-5753, 01-310-5753, 5962013105753, 013105753
| Supply Group (FSG) | NSN Assigned | NIIN | Item Name Code (INC) |
|---|---|---|---|
| 59 | NOV 08, 1989 | 01-310-5753 | 31779 ( MICROCIRCUIT, DIGITAL ) |
REFERENCE DRAWINGS & PICTURES
Cross Reference | NSN 5962-01-310-5753
| Part Number | Cage Code | Manufacturer |
|---|---|---|
| CD54HCT4046AF/3A | 18714 | HARRIS CORPFINDLAY OPNS |
| 77A110638P001 | 03538 | LOCKHEED MARTIN CORPORATIONDIV RMS |
Technical Data | NSN 5962-01-310-5753
| Characteristic | Specifications |
|---|---|
| OUTPUT LOGIC FORM | COMPLEMENTARY-METAL OXIDE-SEMICONDUCTOR LOGIC |
| DESIGN FUNCTION AND QUANTITY | 1 PHASE LOCKED LOOP |
| INPUT CIRCUIT PATTERN | 3 INPUT |
| VOLTAGE RATING AND TYPE PER CHARACTERISTIC | ACVM0.5 VOLTS MINIMUM AND ACV7.0 VOLTS MAXIMUM |
| OPERATING TEMP RANGE | -55.0 TO +125.0 DEG CELSIUS |
| TERMINAL TYPE AND QUANTITY | 16 PRINTED CIRCUIT |
| TERMINAL SURFACE TREATMENT | SOLDER |
| INCLOSURE CONFIGURATION | DUAL-IN-LINE |
| INCLOSURE MATERIAL | CERAMIC |
| CASE OUTLINE SOURCE AND DESIGNATOR | D-2 MIL-M-38510 |
| BODY LENGTH | 0.840 INCHES MAXIMUM |
| BODY HEIGHT | 0.140 INCHES MINIMUM AND 0.185 INCHES MAXIMUM |
| BODY WIDTH | 0.220 INCHES MINIMUM AND 0.310 INCHES MAXIMUM |
| MAXIMUM POWER DISSIPATION RATING | 500.0 MILLIWATTS |
| STORAGE TEMP RANGE | -65.0 TO +150.0 DEG CELSIUS |
| FEATURES PROVIDED | HERMETICALLY SEALED AND BURN IN AND HIGH SPEED AND POSITIVE OUTPUTS AND W/INHIBIT |
| TEST DATA DOCUMENT | 96906-MIL-STD-883 STANDARD (INCLUDES INDUSTRY OR ASSOCIATION STANDARDS, INDIVIDUAL MANUFACTUREER STANDARDS, ETC.). |
| END ITEM IDENTIFICATION | CLASSIFYING-DETECTING SET,MINE AN/SQQ-30 |